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Designing the MPC105 PCI Bridge/Memory Controller
April 1995 (vol. 15 no. 2)
pp. 44-49
The design of a single chip PowerPC Reference Platform Specification compliant bridge between a PowerPC microprocessor and the PCI bus is described. The MPC105 PCI Bridge/Memory Controller allows system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC105 also integrates a secondary cache controller and a high performance memory controller which supports DRAM or SDRAM and ROM or Flash ROM. This article highlights the design features and discusses the architecture, performance, package technology, power management, and physical implementation.
Index Terms:
microprocessors, PowerPC, PCI bus, memory controllers
Citation:
Karl Wang, Chris Bryant, Mike Carlson, Mike Elmer, Adrian Harris, Michael Garcia, C. S. Hui, C. K. Leung, Brian Reynolds, Raymond Tang, Laura Weber, Jim Wenzel, Glen Wilson, Mike Becker, "Designing the MPC105 PCI Bridge/Memory Controller," IEEE Micro, vol. 15, no. 2, pp. 44-49, April 1995, doi:10.1109/40.372351
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