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Superscalar Instruction Execution in the 21164 Alpha Microprocessor
April 1995 (vol. 15 no. 2)
pp. 33-43
| ASCII Text | x | ||
| John H. Edmondson, Paul Rubinfeld, Ronald Preston, Vidya Rajagopalan, "Superscalar Instruction Execution in the 21164 Alpha Microprocessor," IEEE Micro, vol. 15, no. 2, pp. 33-43, April, 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/40.372349, author = {John H. Edmondson and Paul Rubinfeld and Ronald Preston and Vidya Rajagopalan}, title = {Superscalar Instruction Execution in the 21164 Alpha Microprocessor}, journal ={IEEE Micro}, volume = {15}, number = {2}, issn = {0272-1732}, year = {1995}, pages = {33-43}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.372349}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Superscalar Instruction Execution in the 21164 Alpha Microprocessor IS - 2 SN - 0272-1732 SP33 EP43 EPD - 33-43 A1 - John H. Edmondson, A1 - Paul Rubinfeld, A1 - Ronald Preston, A1 - Vidya Rajagopalan, PY - 1995 KW - microprocessors KW - superscalar chips KW - memory KW - multilevel caches VL - 15 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.372349
The 21164 is a new quad-issue superscalar Alpha microprocessor. This new high-performance chip can execute 1.2 billion instructions per second. The part became available in January of 1995 and delivered SPECint92/SPECfp92 performance of 335/500 (estimated), performance unmatched by other commercially available microprocessors. It is implemented in 0.5 micron CMOS and the CPU clock speed is 300 MHz. Instruction execution is controlled by the quad-issue superscalar instruction unit. There are two 64-bit integer execution pipelines and two 64-bit floating-point pipelines. Memory instructions are initiated in the integer pipelines and are completed by the memory and bus interface units that together implement a high-throughput memory subsystem employing a multi-level cache hierarchy.
Index Terms:
microprocessors, superscalar chips, memory, multilevel caches
Citation:
John H. Edmondson, Paul Rubinfeld, Ronald Preston, Vidya Rajagopalan, "Superscalar Instruction Execution in the 21164 Alpha Microprocessor," IEEE Micro, vol. 15, no. 2, pp. 33-43, April 1995, doi:10.1109/40.372349
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