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Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors Part 2
December 1994 (vol. 14 no. 6)
pp. 61-66

Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors.

Citation:
Milo Tomasevic, Veljko Milutinovic, "Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors Part 2," IEEE Micro, vol. 14, no. 6, pp. 61-66, Dec. 1994, doi:10.1109/40.331392
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