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An Analog Systolic Neural Processing Architecture
June 1994 (vol. 14 no. 3)
pp. 51-59
ASCII Text
x 
 
Juan M. Moreno, Francisco Castillo, Joan Cabestany, Jordi Madrenas, Andrezj Napieralski, "An Analog Systolic Neural Processing Architecture," IEEE Micro, vol. 14, no. 3, pp. 51-59, June, 1994.
 
 
BibTex
x
 
@article{ 10.1109/40.285224,
author = {Juan M. Moreno and Francisco Castillo and Joan Cabestany and Jordi Madrenas and Andrezj Napieralski},
title = {An Analog Systolic Neural Processing Architecture},
journal ={IEEE Micro},
volume = {14},
number = {3},
issn = {0272-1732},
year = {1994},
pages = {51-59},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.285224},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - An Analog Systolic Neural Processing Architecture
IS - 3
SN - 0272-1732
SP51
EP59
EPD - 51-59
A1 - Juan M. Moreno,
A1 - Francisco Castillo,
A1 - Joan Cabestany,
A1 - Jordi Madrenas,
A1 - Andrezj Napieralski,
PY - 1994
VL - 14
JA - IEEE Micro
ER -
 

Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.

Citation:
Juan M. Moreno, Francisco Castillo, Joan Cabestany, Jordi Madrenas, Andrezj Napieralski, "An Analog Systolic Neural Processing Architecture," IEEE Micro, vol. 14, no. 3, pp. 51-59, June 1994, doi:10.1109/40.285224
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