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Designing the TFP Microprocessor
April 1994 (vol. 14 no. 2)
pp. 23-33

Designed to efficiently support large, real-world, floating-point-intensive applications, the TFP (short for Tremendous Floating-Point) microprocessor is a superscalar implementation of the Mips Technologies architecture. This floating-point, computation-oriented processor uses a superscalar machine organization that dispatches up to four instructions each clock cycle to two floating-point execution units, two memory load/store units, and two integer execution units. Its split-level cache structure reduces cache misses by directing integer data references to a 16-Kbyte on-chip cache, while channeling floating-point data references off chip to a 4 Mbyte cache.

Citation:
Peter-Yan-Tek Hsu, "Designing the TFP Microprocessor," IEEE Micro, vol. 14, no. 2, pp. 23-33, April 1994, doi:10.1109/40.272835
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