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The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation
September/October 1993 (vol. 13 no. 5)
pp. 24-36
| ASCII Text | x | ||
| Makoto Awaga, Hiromasa Takahashi, "The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation," IEEE Micro, vol. 13, no. 5, pp. 24-36, September/October, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/40.237999, author = {Makoto Awaga and Hiromasa Takahashi}, title = {The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation}, journal ={IEEE Micro}, volume = {13}, number = {5}, issn = {0272-1732}, year = {1993}, pages = {24-36}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.237999}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation IS - 5 SN - 0272-1732 SP24 EP36 EPD - 24-36 A1 - Makoto Awaga, A1 - Hiromasa Takahashi, PY - 1993 VL - 13 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.237999
The architecture and design of the μVP, a single-chip vector coprocessor developed to meet the needs of high-performance processors, are described. The μVP is a supercomputer component implemented on a single large-scale-integrated (LSI) CMOS chip. With 206 MFLOPS single-precision and 106-MFLOPS double-precision performance at 50 MHz, the μVP offers a rate almost equivalent to that typical minisupercomputers.
Citation:
Makoto Awaga, Hiromasa Takahashi, "The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation," IEEE Micro, vol. 13, no. 5, pp. 24-36, Sept.-Oct. 1993, doi:10.1109/40.237999
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