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The Gmicro/500 Superscalar Microprocessor with Branch Buffers
September/October 1993 (vol. 13 no. 5)
pp. 12-22

The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.

Citation:
Kunio Uchiyama, Fumio Arakawa, Susumu Narita, Hirokazu Aoki, Ikuya Kawasaki, Shigezumi Matsui, Mitsuyoshi Yamamoto, Norio Nakagawa, Ikuo Kudo, "The Gmicro/500 Superscalar Microprocessor with Branch Buffers," IEEE Micro, vol. 13, no. 5, pp. 12-22, Sept.-Oct. 1993, doi:10.1109/40.237998
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