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Architecture of the Pentium Microprocessor
May/June 1993 (vol. 13 no. 3)
pp. 11-21

The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8- mu m BiCMOS technology, are described. The technology improvements associated with the three most recent microprocessor generations are outlined. The Pentium's compatibility, performance, organization, and development process are also described. The compiler technology developed with the Pentium microprocessor, which includes machine-independent optimizations common to current high-performance compilers, such as inlining, unrolling, and other loop transformations, is reviewed.

Citation:
Donald Alpert, Dror Avnon, "Architecture of the Pentium Microprocessor," IEEE Micro, vol. 13, no. 3, pp. 11-21, May-June 1993, doi:10.1109/40.216745
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