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Architecture and Implementation of ICs for a DSC-HDTV Video Decoder System
September/October 1992 (vol. 12 no. 5)
pp. 22-27

The architecture and implementation of the very-large-scale integrated (VLSI) video decoder subsystems in digital spectrum compatible high-definition television (DSC-HDTV) systems are discussed. The CMOS deformatter IC, which converts formatted data back to motion vectors, DCT coefficients, and coding parameters, and the motion compensator and inverse discrete transform IC, which reconstructs frames from the deformatter-decoded coefficients, are described.

Citation:
Obed Duardo, Scott C. Knauer, John N. Mailhot, Kalyan Mondal, Tommy C. Poon, "Architecture and Implementation of ICs for a DSC-HDTV Video Decoder System," IEEE Micro, vol. 12, no. 5, pp. 22-27, Sept.-Oct. 1992, doi:10.1109/40.166709
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