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Floating-Point Processors Join Forces in Parallel Processing Architectures
July/August 1992 (vol. 12 no. 4)
pp. 60-69

The hardware architecture and software capabilities of the TMS320C40 floating-point digital signal processor are described. The C40 operates at 275 million operations per second (MOPS) and transfers data at a rate of 320 Mbytes/s with a 40-ns cycle time. A key architectural feature of the C40 for parallel computing is the six parallel bidirectional communication ports that permit direct connection and communication between processors in a parallel system. Examples illustrating the use of the C40 in a parallel processing environment are discussed.

Citation:
Ray Simar, Jr., Peter Koeppen, Jerald Leach, Steve Marshall, Dave Francis, Greg Mekras, Jeffrey Rosenstrauch, Scott Anderson, "Floating-Point Processors Join Forces in Parallel Processing Architectures," IEEE Micro, vol. 12, no. 4, pp. 60-69, July-Aug. 1992, doi:10.1109/40.149737
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