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An Associative Processing Module for a Heterogeneous Vision Architecture
May/June 1992 (vol. 12 no. 3)
pp. 42-55

The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented.

Citation:
Richard Storer, Mike R. Pout, Andrew R. Thomson, Erik L. Dagless, Andrew W.G. Duller, A. Paul Marriott, Peter J. Hick, "An Associative Processing Module for a Heterogeneous Vision Architecture," IEEE Micro, vol. 12, no. 3, pp. 42-55, May-June 1992, doi:10.1109/40.141602
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