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Issue No.02 - March/April (1992 vol.12)
pp: 40-63
ABSTRACT
<p>Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described.</p>
CITATION
"Organization of the Motorola 88110 Superscalar RISC Microprocessor", IEEE Micro, vol.12, no. 2, pp. 40-63, March/April 1992, doi:10.1109/40.127582
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