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A Fine-Grain Architecture for Relational Database Aggregation Operations
November/December 1991 (vol. 11 no. 6)
pp. 35-43

The design and simulation of a bit-sliced processor for relational database aggregation functions, are discussed. The processor, which addresses an important, computationally expensive problem in database computers, takes two tuples as input (one bit at a time) and returns two bits as output every clock cycle. A larger aggregation unit uses a number of identical slice processors, connected according to odd-even network topology, to achieve improved performance on a parallel pipelined processor. The data processing time is completely overlapped with the input and output of data to and from the unit. The design is independent of the tuple size, and since a bit-serial computation is used, the system requires limited interconnection.

Citation:
M. Abdelguerfi, A.K. Sood, "A Fine-Grain Architecture for Relational Database Aggregation Operations," IEEE Micro, vol. 11, no. 6, pp. 35-43, Nov.-Dec. 1991, doi:10.1109/40.108571
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