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Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels
July/August 1991 (vol. 11 no. 4)
pp. 16-19, 50-61
ASCII Text
x 
 
Akira Fukuda, Kazuaki Murakami, Shinji Tomita, "Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels," IEEE Micro, vol. 11, no. 4, pp. 16-19, 50-61, July/August, 1991.
 
 
BibTex
x
 
@article{ 10.1109/40.85721,
author = {Akira Fukuda and Kazuaki Murakami and Shinji Tomita},
title = {Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels},
journal ={IEEE Micro},
volume = {11},
number = {4},
issn = {0272-1732},
year = {1991},
pages = {16-19, 50-61},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.85721},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels
IS - 4
SN - 0272-1732
SP16
EP19, 50-61
EPD - 16-19, 50-61
A1 - Akira Fukuda,
A1 - Kazuaki Murakami,
A1 - Shinji Tomita,
PY - 1991
VL - 11
JA - IEEE Micro
ER -
 

The status of two projects that entail the development of a reconfigurable parallel processor system with 128 Sparc microprocessors and a superscalar processor with four operations proceeding in parallel is discussed. The design principles, system configuration, processing element, network architecture, and memory architecture of the reconfigurable processors (called KRPP) are described. The operating system for KRPP is discussed. The architecture for the superscalar (called a dynamically hazard-resolved, statically code-scheduled, nonuniform superscalar) is presented.

Citation:
Akira Fukuda, Kazuaki Murakami, Shinji Tomita, "Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels," IEEE Micro, vol. 11, no. 4, pp. 16-19, 50-61, July-Aug. 1991, doi:10.1109/40.85721
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