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IBM RISC System/6000: Architecture and Performance
May/June 1991 (vol. 11 no. 3)
pp. 14-17, 56-62

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.

Citation:
Richard R. Oehler, Michael W. Blasgen, "IBM RISC System/6000: Architecture and Performance," IEEE Micro, vol. 11, no. 3, pp. 14-17, 56-62, May-June 1991, doi:10.1109/40.87565
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