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The Metaflow Architecture
May/June 1991 (vol. 11 no. 3)
pp. 10-13, 63-73

The Metaflow architecture, a unified approach to maximizing the performance of superscalar microprocessors, is introduced. The Metaflow architecture exploits inherent instruction-level parallelism in conventional sequential programs by hardware means, without relying on optimizing compilers. It is based on a unified structure, the DRIS (deferred-scheduling, register-renaming instruction shelf), that manages out-of-order execution and most of the attendant problems. Coupling the DRIS with a speculative-execution mechanism that avoids conditional branch stalls results in performance limited only be inherent instruction-level parallelism and available execution resources. Although presented in the context of superscalar machines, the technique is equally applicable to a superpipelined implementation. Lightning, the first implementation of the Metaflow architecture, which executes the Sparc RISC instruction set is described.

Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, David Isaman, "The Metaflow Architecture," IEEE Micro, vol. 11, no. 3, pp. 10-13, 63-73, May-June 1991, doi:10.1109/40.87564
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