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Parallel CRC Generation
September/October 1990 (vol. 10 no. 5)
pp. 63-71

Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.

Citation:
Guido Albertengo, Riccardo Sisto, "Parallel CRC Generation," IEEE Micro, vol. 10, no. 5, pp. 63-71, Sept.-Oct. 1990, doi:10.1109/40.60527
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