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Parallel CRC Generation
September/October 1990 (vol. 10 no. 5)
pp. 63-71
| ASCII Text | x | ||
| Guido Albertengo, Riccardo Sisto, "Parallel CRC Generation," IEEE Micro, vol. 10, no. 5, pp. 63-71, September/October, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/40.60527, author = {Guido Albertengo and Riccardo Sisto}, title = {Parallel CRC Generation}, journal ={IEEE Micro}, volume = {10}, number = {5}, issn = {0272-1732}, year = {1990}, pages = {63-71}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.60527}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Parallel CRC Generation IS - 5 SN - 0272-1732 SP63 EP71 EPD - 63-71 A1 - Guido Albertengo, A1 - Riccardo Sisto, PY - 1990 VL - 10 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.60527
Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.
Citation:
Guido Albertengo, Riccardo Sisto, "Parallel CRC Generation," IEEE Micro, vol. 10, no. 5, pp. 63-71, Sept.-Oct. 1990, doi:10.1109/40.60527
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