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Hierarchical Discrete-Event Simulation on Hypercube Architectures
July/August 1990 (vol. 10 no. 4)
pp. 10-20
ASCII Text
x 
 
Roger D. Chamberlain, Mark A. Franklin, "Hierarchical Discrete-Event Simulation on Hypercube Architectures," IEEE Micro, vol. 10, no. 4, pp. 10-20, July/August, 1990.
 
 
BibTex
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@article{ 10.1109/40.57727,
author = {Roger D. Chamberlain and Mark A. Franklin},
title = {Hierarchical Discrete-Event Simulation on Hypercube Architectures},
journal ={IEEE Micro},
volume = {10},
number = {4},
issn = {0272-1732},
year = {1990},
pages = {10-20},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.57727},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Hierarchical Discrete-Event Simulation on Hypercube Architectures
IS - 4
SN - 0272-1732
SP10
EP20
EPD - 10-20
A1 - Roger D. Chamberlain,
A1 - Mark A. Franklin,
PY - 1990
VL - 10
JA - IEEE Micro
ER -
 

The simulation of systems that include components at varying levels of abstraction is addressed. A performance model of a hierarchical discrete-event simulation algorithm running on a hypercube architecture is presented. The model allows the performance impact of decisions made in the design of the parallel processor as well as in the design of the simulation algorithm to be examined. Three static component partitioning strategies are considered: random partitioning, heuristic partitioning, and simulated annealing. The performance model is applied to digital system simulation.

Citation:
Roger D. Chamberlain, Mark A. Franklin, "Hierarchical Discrete-Event Simulation on Hypercube Architectures," IEEE Micro, vol. 10, no. 4, pp. 10-20, July-Aug. 1990, doi:10.1109/40.57727
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