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The Gmicro/300 32-Bit Microprocessor
May/June 1990 (vol. 10 no. 3)
pp. 68-75

A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300's pipeline structure, its other one-cycle structures, and the effects of using internal caches are discussed.

Citation:
Takeshi Kitahara, Taizo Satoh, "The Gmicro/300 32-Bit Microprocessor," IEEE Micro, vol. 10, no. 3, pp. 68-75, May-June 1990, doi:10.1109/40.56326
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