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Motorola's 88000 Family Architecture
May/June 1990 (vol. 10 no. 3)
pp. 48-66

The initial members of the 88000 family of high-performance 32-bit microprocessor are the 88100 processor and the 88200 cache and memory management unit (CMMU). The processor manipulates integer and floating-point data and initiates instruction and data memory transactions. The CMMU minimizes the latency of main memory requests by maintaining a cache for data transaction and a cache for memory management translations. A typical system consists of one processor and two identical cache chips, one servicing instruction fetch requests, the other servicing data read and write requests. The overall design process for the 88000 family is described, and the integer instructions are discussed. Decisions made with respect to the processor, cache, and software are examined. Some data on the use of the instruction set by the available compilers and the efficiency of the cache and memory systems are presented.

Citation:
Mitch Alsup, "Motorola's 88000 Family Architecture," IEEE Micro, vol. 10, no. 3, pp. 48-66, May-June 1990, doi:10.1109/40.56325
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