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A 4-bit, 250-MIPS Processor Using Josephson Technology
March/April 1990 (vol. 10 no. 2)
pp. 40-55

An experimental 4-bit Josephson processor that demonstrates the possibility of a Josephson computer system with a gigahertz clock is presented. Constructed from 2066 gates on a 5-mm*5-mm die, it implements an eight-instruction set to enable the basic operations of digital signal processing. The basic structure and operating principles of the Josephson device are reviewed, and the design of and operating results for the processor are presented. The focus is mainly on the circuit techniques required to realize a gigahertz clock in a Josephson processor. Circuit techniques to suppress the crosstalk from the AC power to the I/O lines and ways to improve the clock frequency are introduced. The problems remaining in the effort to enhance performance are discussed.

Citation:
Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe, "A 4-bit, 250-MIPS Processor Using Josephson Technology," IEEE Micro, vol. 10, no. 2, pp. 40-55, March-April 1990, doi:10.1109/40.52946
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