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Processing Element Design for a Parallel Computer
March/April 1990 (vol. 10 no. 2)
pp. 26-38

A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two for processor elements (PES) and two for the interprocessor network (plus some memory chips). An overview of ADENA and an analysis of its performance are given. The design considerations for the PEs incorporated in ADENA are discussed. The factors that limit performance in a parallel processing environment are analyzed, and the measures employed to improve these factors at the LSI design level are described. The 42.6 sq cm CMOS PEs reach a peak performance of 20 MFLOPS and a 256-PE ADENA 1.5 GFLOPS has been achieved and 300 to 400 MFLOPS for PDE applications.

Citation:
Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota, "Processing Element Design for a Parallel Computer," IEEE Micro, vol. 10, no. 2, pp. 26-38, March-April 1990, doi:10.1109/40.52945
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