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| Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima, "The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory," IEEE Micro, vol. 10, no. 2, pp. 14-25, March/April, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/40.52944, author = {Hideto Hidaka and Yoshio Matsuda and Mikio Asakura and Kazuyasu Fujishima}, title = {The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory}, journal ={IEEE Micro}, volume = {10}, number = {2}, issn = {0272-1732}, year = {1990}, pages = {14-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.52944}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory IS - 2 SN - 0272-1732 SP14 EP25 EPD - 14-25 A1 - Hideto Hidaka, A1 - Yoshio Matsuda, A1 - Mikio Asakura, A1 - Kazuyasu Fujishima, PY - 1990 VL - 10 JA - IEEE Micro ER - | |||
A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. Suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cache scheme. It is shown how the cache DRAM bridges the gap in speed between high-performance microprocessor units and existing DRAMs. The cache DRAM concept is explained, and its architecture is presented. The error checking and correction scheme used to improve the cache DRAM's reliability is described. Performance results for an experimental device are reported