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An Efficient Scheme for Interprocessor Communication Using Dual-Ported RAMs
September/October 1989 (vol. 9 no. 5)
pp. 10-19

An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use intermediate buffers, input/output ports, or DMAs. The example of a three-dimensional cube is used to illustrate the advantages of this scheme. The implementation of the interprocessor communication scheme on a 64-node cube configuration is discussed

Citation:
N. Jagadish, J. Mohan Kumar, L.M. Patnaik, "An Efficient Scheme for Interprocessor Communication Using Dual-Ported RAMs," IEEE Micro, vol. 9, no. 5, pp. 10-19, Sept.-Oct. 1989, doi:10.1109/40.45822
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