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Issue No.03 - May/June (1989 vol.9)
pp: 26-44
ABSTRACT
<p>A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.</p>
CITATION
Mitsuru Watabe, Shumpei Kawasaki, "A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming", IEEE Micro, vol.9, no. 3, pp. 26-44, May/June 1989, doi:10.1109/40.31476
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