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Issue No.01 - January/February (1989 vol.9)
pp: 57-65
ABSTRACT
<p>The design principles of reduced-instruction-set computer (RISC) architectures as they apply to VLSI implementation for high-level languages (HLLs) are presented. The nature of general-purpose HLL computations is discussed in terms of static and dynamic program measurements, and the HLL features that need efficient support are identified. CISC (complex-instruction-set computer) and RISC approaches to general-purpose HLL computers are outlined, the effects of instruction-set reduction on both code size and execution time are evaluated, and the delayed-jump concept is introduced. The Berkeley RISC architecture is presented as an example.</p>
CITATION
Beatrice Lazzerini, "Effective VLSI Processor Architectures for HLL Computers: The RISC Approach", IEEE Micro, vol.9, no. 1, pp. 57-65, January/February 1989, doi:10.1109/40.16794
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