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Intel's 80960: An Architecture Optimized for Embedded Control
May/June 1988 (vol. 8 no. 3)
pp. 63-76

Important features and capabilities of the 80960 are briefly examined, and an overview of its architecture is given. A detached discussion is presented of the register model, core instruction set, register operations, memory operations, control operations instruction cache, user-supervisor protection, interrupts, faults, and debug support.

Citation:
David P. Ryan, "Intel's 80960: An Architecture Optimized for Embedded Control," IEEE Micro, vol. 8, no. 3, pp. 63-76, May-June 1988, doi:10.1109/40.541
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