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The MIPS R3010 Floating-Point Coprocessor
May/June 1988 (vol. 8 no. 3)
pp. 53-62

A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its architecture is examined. The organization and implementation of the R3010 is discussed.

Citation:
Chris Rowen, Mark Johnson, Paul Ries, "The MIPS R3010 Floating-Point Coprocessor," IEEE Micro, vol. 8, no. 3, pp. 53-62, May-June 1988, doi:10.1109/40.540
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