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Introducing Tobus: the System Bus in the TRON Architecture
March/April 1988 (vol. 8 no. 2)
pp. 47-59
| ASCII Text | x | ||
| Ken Sakamura, Royichi Sano, Kazuhiko Honma, "Introducing Tobus: the System Bus in the TRON Architecture," IEEE Micro, vol. 8, no. 2, pp. 47-59, March/April, 1988. | |||
| BibTex | x | ||
| @article{ 10.1109/40.529, author = {Ken Sakamura and Royichi Sano and Kazuhiko Honma}, title = {Introducing Tobus: the System Bus in the TRON Architecture}, journal ={IEEE Micro}, volume = {8}, number = {2}, issn = {0272-1732}, year = {1988}, pages = {47-59}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.529}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Introducing Tobus: the System Bus in the TRON Architecture IS - 2 SN - 0272-1732 SP47 EP59 EPD - 47-59 A1 - Ken Sakamura, A1 - Royichi Sano, A1 - Kazuhiko Honma, PY - 1988 VL - 8 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.529
The Japanese TRON (The Real-Time Operating Nucleus) project has as its goal the design of a computer architecture that includes a CPU, operating systems and a man-machine interface. Peripherals are portable because TRON designers set a board-level standard for the system bus protocol. The end product transfers data at rates from 50 M to 100 M bytes/s. A description is given of Tobus, the system bus designed to fit the standard. Bus arbitration, data transfer and interrupt-handling are discussed.
Citation:
Ken Sakamura, Royichi Sano, Kazuhiko Honma, "Introducing Tobus: the System Bus in the TRON Architecture," IEEE Micro, vol. 8, no. 2, pp. 47-59, March-April 1988, doi:10.1109/40.529
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