This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Realization of Gmicro/200
March/April 1988 (vol. 8 no. 2)
pp. 12-21

The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200.

Citation:
Hideo Inayoshi, Ikuya Kawasaki, Tadahiko Nishimukai, Ken Sakamura, "Realization of Gmicro/200," IEEE Micro, vol. 8, no. 2, pp. 12-21, March-April 1988, doi:10.1109/40.526
Usage of this product signifies your acceptance of the Terms of Use.