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Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer
January/February 1987 (vol. 7 no. 1)
pp. 60-72
| ASCII Text | x | ||
| Kevin McNeley, Veljko Milutinovic, "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer," IEEE Micro, vol. 7, no. 1, pp. 60-72, January/February, 1987. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.1987.304939, author = {Kevin McNeley and Veljko Milutinovic}, title = {Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer}, journal ={IEEE Micro}, volume = {7}, number = {1}, issn = {0272-1732}, year = {1987}, pages = {60-72}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.1987.304939}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer IS - 1 SN - 0272-1732 SP60 EP72 EPD - 60-72 A1 - Kevin McNeley, A1 - Veljko Milutinovic, PY - 1987 KW - null VL - 7 JA - IEEE Micro ER - | |||
GaAs now allows up to 30K transistors per chip. With such a limitation, can you build a 32-bit CISC on a single GaAs chip? Yes, if you build a reduced instruction set computer and emulate the 32-bit CISC on it.
Citation:
Kevin McNeley, Veljko Milutinovic, "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer," IEEE Micro, vol. 7, no. 1, pp. 60-72, Jan.-Feb. 1987, doi:10.1109/MM.1987.304939
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