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?Designer? Logic And Symbols with Logic Cell Arrays
January/February 1987 (vol. 7 no. 1)
pp. 51-59
| ASCII Text | x | ||
| Steve Landry, "?Designer? Logic And Symbols with Logic Cell Arrays," IEEE Micro, vol. 7, no. 1, pp. 51-59, January/February, 1987. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.1987.304937, author = {Steve Landry}, title = {?Designer? Logic And Symbols with Logic Cell Arrays}, journal ={IEEE Micro}, volume = {7}, number = {1}, issn = {0272-1732}, year = {1987}, pages = {51-59}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.1987.304937}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - ?Designer? Logic And Symbols with Logic Cell Arrays IS - 1 SN - 0272-1732 SP51 EP59 EPD - 51-59 A1 - Steve Landry, PY - 1987 KW - null VL - 7 JA - IEEE Micro ER - | |||
Logic cell arrays allow ASIC designers to create new logic elements and to devise symbols for them that simplify logic schematics.
Citation:
Steve Landry, "?Designer? Logic And Symbols with Logic Cell Arrays," IEEE Micro, vol. 7, no. 1, pp. 51-59, Jan.-Feb. 1987, doi:10.1109/MM.1987.304937
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