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The Design And Implementation of the MC68851 Paged Memory Management Unit
March/April 1986 (vol. 6 no. 2)
pp. 13-28
Brad Cohen, Motorola Microprocessor Products Division
Ralph McGarity, Motorola Microprocessor Products Division
Pipelining, microsequencer start-up in parallel with bus arbitration, and a fully associative translation cache enhanced the performance of this 32-bit memory management device.
Citation:
Brad Cohen, Ralph McGarity, "The Design And Implementation of the MC68851 Paged Memory Management Unit," IEEE Micro, vol. 6, no. 2, pp. 13-28, March-April 1986, doi:10.1109/MM.1986.304739
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