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Scan-based Speed-path Debug for a Microprocessor
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ISSN: 0740-7475
Jing Zeng, AMD, austin
Ruifeng Guo, mentor graphics, wilsonville
Wu-Tung Cheng, mentor graphics, wilsonville
Michael Mateja, Advanced Micro Devices, Austin
Jing Wang, Advanced Micro Devices, Austin
Speed-path debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speed-path debug based on functional patterns can be very expensive. In this paper, we explore speed-path debug techniques based on at-speed scan test patterns. Enhancements are implemented to improve over an earlier proposed scan-based speed-path diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high-performance microprocessor design.
Index Terms:
B.2.3.a Diagnostics, B.2.3.d Test generation, B.2.3.d Test generation, B.2.3.a Diagnostics, B Hardware, B.6.2 Reliability and Testing, Hardware reliability, Built-in tests, design-for test, B Hardware, B.1.3 Control Structure Reliability, Testing, and Fault-Tolerance, B.1.3.a Diagnostics,
Citation:
Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, "Scan-based Speed-path Debug for a Microprocessor," IEEE Design & Test of Computers, 13 June 2011. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MDT.2011.73>
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