Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase on a portion of the clock tree. This paper proposes a novel layout-aware scan segmentation design scheme called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation) for avoiding shift timing failures. The proposed scheme searches for an optimal combination of scan segments for simultaneous clocking so as to reduce the switching activity in the proximities of clock trees while maintaining the average power reduction effect of the conventional scan segmentation. Experimental results on benchmark circuits have demonstrated the advantage of the LCTI-SS scheme.