Issue No.02 - April (2013 vol.30)
Kan Xiao , ECE Dept., Univ. of Connecticut, Storrs, CT, USA
Xuehui Zhang , ECE Dept., Univ. of Connecticut, Storrs, CT, USA
Mohammad Tehranipoor , ECE Dept., Univ. of Connecticut, Storrs, CT, USA
Clock sweeping can be used to generate signatures for the purpose of detecting hardware Trojans. With the help of simulations and FPGA results, this article demonstrates the effectiveness of their proposed clock-sweeping technique under process variations, even for Trojans as small as a few gates.
invasive software, clocks, delay circuits, digital signatures, field programmable gate arrays, process variation, circuit delay, signature, hardware Trojan detection, FPGA, clock-sweeping technique, Trojan horses, Computer security, Delays, Payloads, Logic gates, Integrated circuits, Synchronization, Circuit layout, outlier analysis, Hardware Trojan, delay-based detection, clock sweeping, process variation, multidimensional scaling
Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor, "A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay", IEEE Design & Test of Computers, vol.30, no. 2, pp. 26-34, April 2013, doi:10.1109/MDAT.2013.2249555