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Issue No.05 - Oct. (2012 vol.29)
pp: 81-93
ABSTRACT
Design-induced systematic defects are serious threats to the semiconductor industry. This paper develops novel techniques to identify and prevent such defects, which facilitate to evaluate the effectiveness of DFM rules and improve the manufacturing process and design for yield enhancement.
INDEX TERMS
semiconductor industry, design for manufacture, integrated circuit design, integrated circuit yield, design-for-manufacturability, integrated circuits, physically-aware analysis, design-induced systematic defects, serious threats, semiconductor industry, DFM rules, manufacturing process, yield enhancement, Systematics, Fault diagnosis, Testing, Integrated circuit modeling, Feature extraction, yield learning, Systematic defects, DFM rule evaluation, layout analysis, volume diagnosis
CITATION
R. D. Blanton, "Physically-Aware Analysis of Systematic Defects in Integrated Circuits", IEEE Design & Test of Computers, vol.29, no. 5, pp. 81-93, Oct. 2012, doi:10.1109/MDT.2012.2211093
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