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Physically-Aware Analysis of Systematic Defects in Integrated Circuits
Oct. 2012 (vol. 29 no. 5)
pp. 81-93
| ASCII Text | x | ||
| Wing Chiu Tam, R. D. Blanton, "Physically-Aware Analysis of Systematic Defects in Integrated Circuits," IEEE Design & Test of Computers, vol. 29, no. 5, pp. 81-93, Oct., 2012. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2012.2211093, author = { Wing Chiu Tam and R. D. Blanton}, title = {Physically-Aware Analysis of Systematic Defects in Integrated Circuits}, journal ={IEEE Design & Test of Computers}, volume = {29}, number = {5}, issn = {0740-7475}, year = {2012}, pages = {81-93}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2211093}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Physically-Aware Analysis of Systematic Defects in Integrated Circuits IS - 5 SN - 0740-7475 SP81 EP93 EPD - 81-93 A1 - Wing Chiu Tam, A1 - R. D. Blanton, PY - 2012 KW - semiconductor industry KW - design for manufacture KW - integrated circuit design KW - integrated circuit yield KW - design-for-manufacturability KW - integrated circuits KW - physically-aware analysis KW - design-induced systematic defects KW - serious threats KW - semiconductor industry KW - DFM rules KW - manufacturing process KW - yield enhancement KW - Systematics KW - Fault diagnosis KW - Testing KW - Integrated circuit modeling KW - Feature extraction KW - yield learning KW - Systematic defects KW - DFM rule evaluation KW - layout analysis KW - volume diagnosis VL - 29 JA - IEEE Design & Test of Computers ER - | |||
Design-induced systematic defects are serious threats to the semiconductor industry. This paper develops novel techniques to identify and prevent such defects, which facilitate to evaluate the effectiveness of DFM rules and improve the manufacturing process and design for yield enhancement.
Index Terms:
semiconductor industry,design for manufacture,integrated circuit design,integrated circuit yield,design-for-manufacturability,integrated circuits,physically-aware analysis,design-induced systematic defects,serious threats,semiconductor industry,DFM rules,manufacturing process,yield enhancement,Systematics,Fault diagnosis,Testing,Integrated circuit modeling,Feature extraction,yield learning,Systematic defects,DFM rule evaluation,layout analysis,volume diagnosis
Citation:
Wing Chiu Tam, R. D. Blanton, "Physically-Aware Analysis of Systematic Defects in Integrated Circuits," IEEE Design & Test of Computers, vol. 29, no. 5, pp. 81-93, Oct. 2012, doi:10.1109/MDT.2012.2211093
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