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Issue No.06 - Nov.-Dec. (2011 vol.28)

pp: 50-57

Youngsoo Shin , KAIST

Seungwhun Paik , Synopsys

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.24

ABSTRACT

<p>Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits.</p>

INDEX TERMS

design and test, pulsed latch, pulsed-latch ASIC methodology, high performance, low power

CITATION

Youngsoo Shin, Seungwhun Paik, "Pulsed-Latch Circuits: A New Dimension in ASIC Design",

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