This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Adaptive Testing: Dealing with Process Variability
Nov.-Dec. 2011 (vol. 28 no. 6)
pp. 41-49
Peter Maxwell, Aptina

This article describes the development of adaptive testing in response to the ever-growing need to dynamically and cost-effectively tailor IC testing to discriminately manage manufacturing process variations. Various degrees of adoption are presented, together with benefits and examples of its use. Finally, challenges for future development are discussed.

1. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits," J. Solid-State Circuits, vol. 40, no. 9, 2005, pp. 1787-1796.
2. J. Segura et al., "Parametric Failures in CMOS ICs—A Defect-Based Analysis," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 90-99.
3. A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer, 2005.
4. Y. Xie and Y. Chen, "Statistical High-Level Synthesis under Process Variability," IEEE Design and Test, vol. 26, no. 4, 2009, pp. 78-87.
5. A. Gattiker and W. Maly, "Current Signatures," Proc. 14th VLSI Test Symp. (VTS 96), IEEE Press, 1996, pp. 112-117.
6. R. Madge et al., "Statistical Post-Processing at Wafer Sort—An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-Micron Technologies," Proc. 20th VLSI Test Symp. (VTS 02), IEEE CS Press, 2002, pp. 69-74.
7. P. Maxwell et al., "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing," Proc. Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, pp. 738-746.
8. International Technology Roadmap for Semiconductors, 2009; http://www.itrs.net/Links/2009ITRSHome2009.htm .
9. R. Madge et al., "Screening MinVDD Outliers Using Feed-Forward Voltage Testing," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 673-682.
10. P.M. O'Neill, "Statistical Test: A New Paradigm to Improve Test Effectiveness and Efficiency," Proc. Int'l Test Conf. (ITC 07), IEEE Press, 2007, paper 3.1, doi:10.1109/TEST.2007.4437700.
11. A. Nahar et al., "Quality Improvement and Cost Reduction Using Statistical Outlier Methods," Proc. Int'l Conf. Computer Design (ICCD 09), IEEE Press, 2009, pp. 64-69.
12. T. Barnett et al., "Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction," Proc. 20th VLSI Test Symp. (VTS 02), IEEE CS Press, 2002, pp. 75-80.
13. A. Gattiker, "Unraveling Variability for Process/Product Improvement," Proc. Int'l Test Conf. (ITC 08), IEEE Press, 2008, paper 1.3, doi:10.1109/TEST.2008. 4700550.
14. G. Smith, "The Challenge of Multisite Test," Test and Measurement World,1 Feb. 2006; http://www.tmworld.com/article318454-The_challenge_of_multisite_test.php .
1. A.D. Singh and C.M. Krishna, "On Optimizing VLSI Testing for Product Quality Using Die-Yield Prediction," IEEE Trans. CAD, IEEE Press, 1993, pp. 695-709.
2. P. Maxwell et al., "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing," Proc. Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, pp. 738-746.
3. A. Gattiker and W. Maly, "Current Signatures," Proc. VLSI Test Symp. (VTS 96), IEEE Press, 1996, pp. 112-117.
4. T.J. Powell et al., "Delta Iddq for Testing Reliability," Proc. VLSI Test Symp., IEEE CS Press, 2000, pp. 439-443.
5. W.R. Daasch and R. Madge, "Variance Reduction and Outliers: Statistical Analysis of Semiconductor Test Data," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, paper 13.1, doi:10.1109/TEST.2005.1583988.
6. Automotive Electronics Council Component Technical Committee, Guidelines for Part Average Testing, tech. report AEC-Q001, Automotive Electronics Council, 2003; http://www.aecouncil.comAECDocuments.html .
7. S. Benner and O. Boroffice, "Optimal Production Test Times through Adaptive Test Programming," Proc. Int'l Test Conf. (ITC 01), IEEE CS Press, 2001, pp. 908-915.
8. E. Yilmaz and S. Ozev, "Adaptive Test Elimination for Analog/RF Circuits," Proc. 46th Design Automation Conf. (DAC 09), ACM Press, 2009, pp. 720-725.
9. E. Yilmaz and S. Ozev, "Adaptive Test Flow for Mixed-Signal Circuits Using Learned Information from Device under Test," Proc. Int'l Test Conf. (ITC 10), IEEE CS Press, 2010, paper 23.1, doi:10.1109/TEST.2010.5699271.
10. A. Nahar et al., "Quality Improvement and Cost Reduction Using Statistical Outlier Methods," Proc. Int'l Conf. Computer Design (ICCD 09), IEEE Press, 2009, pp. 64-69.

Index Terms:
design and test, variability, statistical data analysis, test flow, real-time analysis
Citation:
Peter Maxwell, "Adaptive Testing: Dealing with Process Variability," IEEE Design & Test of Computers, vol. 28, no. 6, pp. 41-49, Nov.-Dec. 2011, doi:10.1109/MDT.2011.118
Usage of this product signifies your acceptance of the Terms of Use.