The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.05 - September/October (2011 vol.28)
pp: 62-71
Rafael Iankowski Soares , Federal University of Pelotas
ABSTRACT
<p>Editors' note:</p><p>This article presents the design of a cryptographic chip using a globally asynchronous, locally synchronous (GALS) design methodology. The design demonstrates the key advantage of using asynchrony in cryptography: the randomization of event timing internal to the chip leads to a dramatic increase in its robustness to side-channel attacks based on power and electromagnetic emission signatures.</p><p align="right">&#x2014;Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)</p>
INDEX TERMS
design and test, GALS, asynchronous, cryptography attacks, SCA, DPA, DEMA
CITATION
Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Rafael Iankowski Soares, "A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines", IEEE Design & Test of Computers, vol.28, no. 5, pp. 62-71, September/October 2011, doi:10.1109/MDT.2011.69
REFERENCES
1. R. Soares et al., "A GALS Pipeline DES Architecture to Increase Robustness against DPA and DEMA Attacks," Proc. 23rd Ann. Symp. Integrated Circuits & System Design (SBCCI 10), ACM Press, 2010, pp. 115-120.
2. F. Gürkaynak et al., "Design Challenges for a Differential- Power-Analysis Aware GALS-based AES Crypto ASIC," Electronic Notes in Theoretical Computer Science, vol. 146, no. 2, 2006, pp. 133-149.
3. Y. Lu, M. O'Neill, and J. McCanny, "FPGA Implementation and Analysis of Random Delay Insertion Countermeasure against DPA," Proc. Int'l Conf. Field-Programmable Technology (FPT 08), IEEE Press, 2008, pp. 201-208.
4. S. Guilley et al., "Area Optimization of Cryptographic Co-processors Implemented in Dual-Rail with Precharge Positive Logic," Proc. Int'l Conf. Field Programmable Logic and Applications (FPL 08), IEEE Press, 2008, pp. 161-166.
5. A. Razafindraibe, M. Robert, and P. Maurine, "Improvement of Dual Rail Logic as a Countermeasure against DPA," Proc. 15th IEEE/IFIP VLSI System on Chip Conf. (VLSI-SOC 07), IEEE Press, 2007, pp. 270-275.
6. K. Kulikowski et al., "Asynchronous Balanced Gates Tolerant to Interconnect Variability," Proc. Int'l Symp. Circuits and Systems (ISCAS 08), IEEE Press, 2008, pp. 3190-3193.
7. D. Shang et al., "High-Security Asynchronous Circuit Implementation of AES," Proc. IEE Computers and Digital Techniques, vol. 153, no. 2, 2006, pp. 71-77.
8. F. Ghellar and M. Lubaszewski, "A Novel AES Cryptographic Core Highly Resistant to Differential Power Analysis," Proc. 21st Ann. Symp. Integrated Circuits & System Design (SBCCI 08), ACM Press, 2008, pp. 140-145.
9. J. Goodwin and P. Wilson, "Advanced Encryption Standard (AES) Implementation with Increased DPA Resistance and Low Overhead," Proc. Int'l Symp. Circuits and Systems (ISCAS 08), IEEE Press, 2008, pp. 3286-3289.
10. T. Popp and S. Mangard, "Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints," Cryptographic Hardware and Embedded Systems (CHES 05), LNCS 3659, Springer, 2005, pp. 172-186.
11. V. Lomné et al., "Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA," Proc. Design, Automation and Test in Europe Conf. (DATE 09), European Design and Automation Assoc., 2009, pp. 634-639.
6 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool