Subscribe

Issue No.05 - September/October (2011 vol.28)

pp: 52-61

Jo Ebergen , Oracle Labs

Daniel Finchelstein , Nvidia

Russell Kao , Oracle Labs

Jon Lexau , Oracle Labs

David Hopkins , Oracle Labs

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.95

ABSTRACT

<p>Editors' note:</p><p>This article presents a case study of a fast and energy-efficient hardware implementation of a stack. The design is highly scalable, as its cycle time remains unchanged and energy per operation grows very slowly, with an increase in the number of storage locations. This design example demonstrates two often-claimed benefits of asynchronous circuit design: the potential for high average-case performance and low power consumption.</p><p align="right">—Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)</p>

INDEX TERMS

design and test, asynchronous circuits, LIFO, stack, static-energy consumption, dynamic-energy consumption

CITATION

Jo Ebergen, Daniel Finchelstein, Russell Kao, Jon Lexau, David Hopkins, "An Evaluation of Asynchronous Stacks",

*IEEE Design & Test of Computers*, vol.28, no. 5, pp. 52-61, September/October 2011, doi:10.1109/MDT.2011.95REFERENCES

- 1. I. Sutherland and S. Fairbanks, "GasP: A Minimal FIFO Control,"
Proc. 7th IEEE Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 01), IEEE CS Press, 2001, pp. 46-53.- 2. J. Ebergen et al., "A Fast and Energy-Efficient Stack,"
Proc. 10th IEEE Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 04), IEEE CS Press, 2004, pp. 7-16.- 3. A.J. Martin, "A Synthesis Method for Self-Timed VLSI Circuits,"
Proc. Int'l Conf. Computer Design (ICCD 87), IEEE CS Press, 1987, pp. 224-229.- 4. M.B. Josephs and J.T. Udding, "Implementing a Stack as a Delay-Insensitive Circuit,"
Proc. IFIP WG10.5 Working Conf. Asynchronous Design Methodologies, North-Holland Publishing Co., 1993, pp. 123-135.- 5. F. Pessolano and M.B. Josephs, "A Low-Power, High-Speed Stack Controller Designed Using Asynchronous Circuit Techniques,"
Proc. 8th Int'l Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS 98), pp. 387-396; http://xputers.informatik.uni-kl.de/conferences/ patmos/patmos98index.html. - 6. B.S. Amrutur and M.A. Horowitz, "Speed and Power Scaling of SRAM's,"
IEEE J. Solid-State Circuits, vol. 35, no. 2, 2000, pp. 175-185.- 7. J. Dama and A. Lines, "GHz Asynchronous SRAM in 65nm,"
Proc. 15th IEEE Symp. Asynchronous Circuits and Systems (ASYNC 09), IEEE CS Press, 2009, pp. 85-94.- 8. J. Ebergen, J. Gainsley, and P. Cunningham, "Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit,"
Proc. 10th IEEE Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 04), IEEE CS Press, 2004, pp. 51-61.- 9. J.L. Peterson,
Petri Net Theory and the Modeling of Systems, Prentice Hall, 1981.- 10. M. McDonnell and K. Winters, "A Dynamically Allocated CMOS Dual-LIFO Register Stack,"
IEEE J. Solid-State Circuits, vol. 25, no. 5, 1990, pp. 1287-1290.- 11. S. Cosemans, W. Dehaene, and F. Catthoor, "A Low-Power Embedded SRAM for Wireless Applications,"
IEEE J. Solid-State Circuits, vol. 42, no. 7, 2007, pp. 1607-1617.- 12. K.W. Mai et al., "Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques,"
IEEE J. Solid-State Circuits, vol. 33, no. 11, 1998, pp. 1659-1671. |