This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Proteus: An ASIC Flow for GHz Asynchronous Designs
September/October 2011 (vol. 28 no. 5)
pp. 36-51
Peter A. Beerel, University of Southern California and Fulcrum Microsystems
Georgios D. Dimou, Fulcrum Microsystems
Andrew M. Lines, Fulcrum Microsystems

Editors' note:

The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.

—Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)

1. A.M. Lines, "Pipelined Asynchronous Circuits," master's thesis, California Inst. of Technology, Record Number Caltech CSTR:1998.cs-tr-95-21, 1995.
2. A. Taubin et al., "Design Automation of Real-Life Asynchronous Devices and Systems," Foundations and Trends in Electronic Design Automation, vol. 2, no. 1, 2007, pp. 1-133.
3. A.M.G. Peeters, "Single-Rail Handshake Circuits," PhD thesis, Eindhoven Univ. of Technology, 1996.
4. I.E. Sutherland, "Micropipelines," Comm. ACM, vol. 32, no. 6, 1989, pp. 720-738.
5. A. Smirnov et al., "An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library," Proc. 5th Int'l Conf. Application of Concurrency to System Design (ACSD 05), IEEE CS Press, 2005, pp. 68-76.
6. P.A. Beerel, M. Ferretti, and R.O. Ozdag, A Designer's Guide to Asynchronous VLSI, Cambridge Univ. Press, 2010.
7. A. Dasdan and R.K. Gupta, "Faster Maximum and Minimum Mean Cycle Algorithms for System-Performance Analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, 1998, pp. 889-899.
8. P.A. Beerel et al., "Slack Matching Asynchronous Designs," Proc. Int'l. Symp. Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 184-194.
9. M. Prakash, "Library Characterization and Static Timing Analysis of Template Based Asynchronous Circuits," master's thesis, Ming Hsieh Dept. of Electrical Eng., Univ. of Southern California, 2007.
10. G. Gill, J. Hansen, and M. Singh, "Loop Pipelining for High-Throughput Stream Computation Using Self-Timed Rings," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), ACM Press, 2006, pp. 289-296.
11. G.D. Dimou, "Clustering and Fanout Optimization for Asynchronous Circuits," doctoral dissertation, Ming Hsieh Dept. of Electrical Eng., Univ. of Southern California, 2009.
12. G. Gill, V. Gupta, and M. Singh, "Performance Estimation and Slack Matching for Pipelined Asynchronous Architectures with Choice," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 08), ACM Press, 2008, pp. 449-456.
13. M. Shreedhar and G. Varghese, "Efficient Fair Queueing Using Deficit Round Robin," ACM SIGCOMM Computer Communication Rev., vol. 25, no. 4, 1995, pp. 231-242.
1. A.M.G. Peeters, "Single-Rail Handshake Circuits," PhD thesis, Eindhoven Univ. of Technology, 1996.
2. A.M. Scott et al., "Asynchronous On-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus," Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC 07), IEEE CS Press, 2007, pp. 60-72.
3. A.J. Martin, M. Nystrom, and C.G. Wong, "Three Generations of Asynchronous Microprocessors," IEEE Design & Test, vol. 20, no. 6, 2003, pp. 9-17.
4. R.O. Ozdag and P.A. Beerel, "An Asynchronous Low-Power High-Performance Sequential Decoder Implemented with QDI Templates," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 14, no. 9, 2006, pp. 975-985.
5. M. Prakash, "Library Characterization and Static Timing Analysis of Template Based Asynchronous Circuits," master's thesis, Ming Hsieh Dept. of Electrical Eng., Univ. of Southern California, 2007.

Index Terms:
design and test, asynchronous design, high performance, slack matching, communicating sequential processes, asynchronous place and route
Citation:
Peter A. Beerel, Georgios D. Dimou, Andrew M. Lines, "Proteus: An ASIC Flow for GHz Asynchronous Designs," IEEE Design & Test of Computers, vol. 28, no. 5, pp. 36-51, Sept.-Oct. 2011, doi:10.1109/MDT.2011.114
Usage of this product signifies your acceptance of the Terms of Use.