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Ran Ginosar, "Metastability and Synchronizers: A Tutorial," IEEE Design & Test of Computers, vol. 28, no. 5, pp. 2335, September/October, 2011.  
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@article{ 10.1109/MDT.2011.113, author = {Ran Ginosar}, title = {Metastability and Synchronizers: A Tutorial}, journal ={IEEE Design & Test of Computers}, volume = {28}, number = {5}, issn = {07407475}, year = {2011}, pages = {2335}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2011.113}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  MGZN JO  IEEE Design & Test of Computers TI  Metastability and Synchronizers: A Tutorial IS  5 SN  07407475 SP23 EP35 EPD  2335 A1  Ran Ginosar, PY  2011 KW  design and test KW  metastability KW  synchronizer KW  FIFO synchronizer KW  mesochronous KW  asynchronous KW  multisynchronous VL  28 JA  IEEE Design & Test of Computers ER   
Editors' note:
Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing domains on a chip. Despite the critical importance of reliable synchronization, this topic remains inadequately understood. This tutorial provides a glimpse into the theory and practice of this fascinating subject.
1. S. Lubkin, "Asynchronous Signals in Digital Computers," Mathematical Tables and Other Aids to Computation (ACM section), vol. 6, no. 40, 1952, pp. 238241.
2. T.J. Chaney and C.E. Molnar, "Anomalous Behavior of Synchronizer and Arbiter Circuits," IEEE Trans. Computers, vol. C22, no. 4, 1973, pp. 421422.
3. D.J. Kinniment and J.V. Woods, "Synchronization and Arbitration Circuits in Digital Systems," Proc. IEE, vol. 123, no. 10, 1976, pp. 961966.
4. H.J.M. Veendrick, "The Behavior of FlipFlops Used as Synchronizers and Prediction of Their Failure Rate," IEEE J. SolidState Circuits, vol. 15, no. 2, 1980, pp. 169176.
5. M. Stucki and J. Cox, "Synchronization Strategies," Proc. 1st Caltech Conf. VLSI, Caltech, 1979, pp. 375393.
6. C. Seitz, "System Timing," Introduction to VLSI Systems, chapter 7, C. Mean and L. Conway, eds., AddisonWesley, 1979.
7. L. Kleeman and A. Cantoni, "Metastable Behavior in Digital Systems," IEEE Design & Test, vol. 4, no. 6, 1987, pp. 419.
8. T. H.Y. Meng, Synchronization Design for Digital Systems, Kluwer Academic Publishers, 1991.
9. D.J. Kinniment, Synchronization and Arbitration in Digital Systems, Wiley, 2008.
10. W.J. Dally and J.W. Poulton, Digital System Engineering, Cambridge Univ. Press, 1998.
11. C. Dike and E. Burton, "Miller and Noise Effects in a Synchronizing FlipFlop," IEEE J. SolidState Circuits, vol. 34, no. 6, 1999, pp. 849855.
12. D.J. Kinniment, A. Bystrov, and A. Yakovlev, "Synchronization Circuit Performance," IEEE J. SolidState Circuits, vol. 37, no. 2, 2002, pp. 202209.
13. S. Yang and M. Greenstreet, "Computing Synchronizer Failure Probabilities," Proc. Design Automation and Test in Europe Conf. (DATE 07), EDAA, 2007, pp. 16.
14. L.S. Kim, R. Cline, and R.W. Dutton, "Metastability of CMOS Latch/FlipFlop," Proc. IEEE Custom Integrated Circuits Conf. (CICC 89), IEEE Press, 1989, pp. 26.3/126.3/4.
15. Y. Semiat and R. Ginosar, "Timing Measurements of Synchronization Circuits," Proc. IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 6877.
16. S. Beer et al., "The Devolution of Synchronizers," Proc. IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 10), IEEE CS Press, 2010, pp. 94103.
17. J. Jones, S. Yang, and M. Greenstreet, "Synchronizer Behavior and Analysis," Proc. IEEE Int'l Symp. Circuits and Systems (ASYNC 09), IEEE CS Press, 2009, pp. 117126.
18. S. Yang and M. Greenstreet, "Simulating Improbable Events," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 154157.
19. C. Cummings, "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog," Proc. Synopsys User Group Meeting (SNUG), 2008; http://www.sunburstdesign.com/papersCummingsSNUG2008Boston_CDC.pdf .
20. T. Chelcea and S.M. Nowick, "Robust Interfaces for Mixed Timing Systems," IEEE Trans. Very large Scale Integration (VLSI) Systems, vol. 12, no. 8, 2004, pp. 857873.
21. R. Dobkin, R. Ginosar, and C. Sotiriou, "High Rate Data Synchronization in GALS SoCs," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 14, no. 10, 2006, pp. 10631074.
22. R. Dobkin and R. Ginosar, "Two Phase Synchronization with SubCycle Latency," Integration, the VLSI J., vol. 42, no. 3, 2009, pp. 367375.
23. J. Zhou et al., "A Robust Synchronizer," Proc. IEEE Symp. Emerging VLSI Technologies and Architectures (ISVLSI 06), IEEE CS Press, 2006, pp. 442443.
24. M. Kayam, R. Ginosar, and C.E. Dike, "Symmetric Boost Synchronizer for Robust Low Voltage, Low Temperature Operation," EE tech. report, Technion, 2007; http://webee.technion.ac.il/~ran/papersKayamGinosarDike25Jan2007.pdf .
25. R. Cline, Method and Circuit for Improving Metastable Resolving Time in LowPower MultiState Devices, US patent 5789945, to Philips Electronics North America Corporation, Patent and Trademark Office, 1998.
26. R. Ginosar and R. Kol, "Adaptive Synchronization," Proc. Int'l Conf. Computer Design (ICCD 98), IEEE CS Press, 1998, pp. 188189.
27. R. Ginosar, "Fourteen Ways to Fool Your Synchronizer," Proc. IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 8996.
28. U. Frank, T. Kapschitz, and R. Ginosar, "A Predictive Synchronizer for Periodic Clock Domains," J. Formal Methods in System Design, vol. 28, no. 2, 2006, pp. 171186.
29. R. Dobkin et al., "Assertion Based Verification of MultipleClock GALS Systems," Proc. IFIP/IEEE Int'l Conf. Very Large Scale Integration (VLSISoC 08), 2008, pp. 152155.
30. E. Beigné et al., "An Asynchronous NOC Architecture Providing Low Latency Service and Its MultiLevel Design Framework," Proc. IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 5463.