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Issue No.05 - September/October (2011 vol.28)
pp: 23-35
Ran Ginosar , Technion—Israel Institute of Technology
<p>Editors' note:</p><p>Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing domains on a chip. Despite the critical importance of reliable synchronization, this topic remains inadequately understood. This tutorial provides a glimpse into the theory and practice of this fascinating subject.</p><p align="right"><it>&#x2014;Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)</it></p>
design and test, metastability, synchronizer, FIFO synchronizer, mesochronous, asynchronous, multisynchronous
Ran Ginosar, "Metastability and Synchronizers: A Tutorial", IEEE Design & Test of Computers, vol.28, no. 5, pp. 23-35, September/October 2011, doi:10.1109/MDT.2011.113
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