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Steven M. Nowick, Montek Singh, "HighPerformance Asynchronous Pipelines: An Overview," IEEE Design & Test of Computers, vol. 28, no. 5, pp. 822, September/October, 2011.  
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@article{ 10.1109/MDT.2011.71, author = {Steven M. Nowick and Montek Singh}, title = {HighPerformance Asynchronous Pipelines: An Overview}, journal ={IEEE Design & Test of Computers}, volume = {28}, number = {5}, issn = {07407475}, year = {2011}, pages = {822}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2011.71}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  MGZN JO  IEEE Design & Test of Computers TI  HighPerformance Asynchronous Pipelines: An Overview IS  5 SN  07407475 SP8 EP22 EPD  822 A1  Steven M. Nowick, A1  Montek Singh, PY  2011 KW  design and test KW  asynchronous KW  pipelines KW  elastic circuits KW  dynamic logic KW  micropipelines KW  latch controllers VL  28 JA  IEEE Design & Test of Computers ER   
Editor's note:
Pipelining is a key element of highperformance design. Distributed synchronization is at the same time one of the key strengths and one of the major difficulties of asynchronous pipelining. It automatically provides elasticity and ondemand power consumption. This tutorial provides an overview of the bestinclass asynchronous pipelining methods that can be used to fully exploit the advantages of this design style, covering both static and dynamic logic implementations.
—Luciano Lavagno, Politecnico di Torino
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1. A.M. Lines, Pipelined Asynchronous Circuits, tech. report, Dept. of Computer Science, California Inst. of Technology, 1998.
2. S.B. Furber and J. Liu, "Dynamic Logic in FourPhase Micropipelines," Proc. 2nd Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 96), IEEE CS Press, 1996, pp. 1116.
3. M. Singh and S.M. Nowick, "The Design of HighPerformance Dynamic Asynchronous Pipelines: Lookahead Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 12561269.
4. M. Singh and S.M. Nowick, "The Design of HighPerformance Dynamic Asynchronous Pipelines: HighCapacity Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 12701283.
5. J. Ebergen et al., "GasP Control for Domino Circuits," Proc. 11th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 1222.
6. M. Ferretti and P.A. Beerel, "High Performance Asynchronous Design Using SingleTrack FullBuffer Standard Cells," IEEE J. SolidState Circuits, vol. 41, no. 6, 2006, pp. 14441454.
7. A. Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, 2004, pp. 3241.
8. M. Singh et al., "An Adaptively Pipelined Mixed SynchronousAsynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, 2010, pp. 10431056.