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High-Performance Asynchronous Pipelines: An Overview
September/October 2011 (vol. 28 no. 5)
pp. 8-22
Steven M. Nowick, Columbia University
Montek Singh, University of North Carolina at Chapel Hill

Editor's note:

Pipelining is a key element of high-performance design. Distributed synchronization is at the same time one of the key strengths and one of the major difficulties of asynchronous pipelining. It automatically provides elasticity and on-demand power consumption. This tutorial provides an overview of the best-in-class asynchronous pipelining methods that can be used to fully exploit the advantages of this design style, covering both static and dynamic logic implementations.

—Luciano Lavagno, Politecnico di Torino

1. I.E. Sutherland, "Micropipelines," Comm. ACM, vol. 32, no. 6, 1989, pp. 720-738.
2. M. Singh and S.M. Nowick, "MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 6, 2007, pp. 684-698.
3. I. Sutherland and S. Fairbanks, "GasP: A Minimal FIFO Control," Proc. 7th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 01), IEEE CS Press, 2001, pp. 46-53.
4. T.E. Williams, "Self-Timed Rings and Their Application to Division," doctoral dissertation, Dept. of Electrical Eng., Stanford Univ., 1991.
5. T.E. Williams and M.A. Horowitz, "A Zero-Overhead Self-Timed 160ns 54b CMOS Divider," IEEE J. Solid-State Circuits, vol. 26, no. 11, 1991, pp. 1651-1661.
6. A.M. Lines, Pipelined Asynchronous Circuits, tech. report no. CaltechCSTR:1998.cs-tr-95-21, Dept. of Computer Science, California Inst. of Technology, 1998.
7. M. Singh and S.M. Nowick, "The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 1270-1283.
8. D.E. Muller, "Asynchronous Logics and Application to Information Processing," Proc. Symp. the Application of Switching Theory to Space Technology, Stanford University Press, 1963, pp. 289-297.
9. C.L. Seitz, "System Timing," Introduction to VLSI Systems, C.A. Mead, and L.A. Conway eds., Addison- Wesley, 1980, pp. 218-262.
10. C. La Frieda, B. Hill, and R. Manohar, "An Asynchronous FPGA with Two-Phase Enable-Scaled Routing," Proc. IEEE Symp. Asynchronous Circuits and Systems (ASYNC 10), IEEE CS Press, 2010, pp. 141-150.
11. A. Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, 2004, pp. 32-41.
12. M. Singh et al., "An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, 2010, pp. 1043-1056.
13. S.M. Nowick et al., "Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders," Proc. 3rd Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 97), IEEE CS Press, 1997, pp. 210-223.
14. L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni- Vincentelli, "Theory of Latency-Insensitive Design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, 2001, pp. 1059-1076.
15. J. Carmona et al., "Elastic Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, 2009, pp. 1437-1455.
16. M.N. Horak et al., "A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, 2011, pp. 494-507.
17. M. Singh and S.M. Nowick, "The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 1256-1269.
18. T. Chelcea and S.M. Nowick, "Robust Interfaces for Mixed-Timing Systems," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, 2004, pp. 857-873.
19. E. Beigne et al., "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-level Design Framework," Proc. 11th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 54-63.
20. A. Sheibanyrad, A. Greiner, and I. Miro-Panades, "Multisynchronous and Fully Asynchronous NoCs for GALS Architectures," IEEE Design & Test, vol. 25, no. 6, 2008, pp. 572-580.
21. M. Choi et al., "Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design," Proc. 21st IEEE Int'l Symp. Defect and Fault-Tolerance in VLSI Systems (DFT 06), IEEE CS Press, 2006, pp. 80-88.
22. W.J. Bainbridge et al., "Delay-Insensitive, Point-to-Point Interconnect Using m-of-n Codes," Proc. 9th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 132-140.
23. S.B. Furber and J. Liu, "Dynamic Logic in Four-Phase Micropipelines," Proc. 2nd Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 96), IEEE CS Press, 1996, pp. 11-16.
24. B. Quinton, M. Greenstreet, and S. Wilton, "Practical Asynchronous Interconnect Network Design," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, 2008, pp. 579-588.
25. P.A. Beerel and A. Xie, "Performance Analysis of Asynchronous Circuits Using Markov Chains," Proc. Concurrency and Hardware Design, LNCS 2549, Springer, 2002, pp. 313-344.
26. J. Ebergen et al., "GasP Control for Domino Circuits," Proc. 11th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 12-22.
27. M. Ferretti and P.A. Beerel, "High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells," IEEE J. Solid-State Circuits, vol. 41, no. 6, 2006, pp. 1444-1454.
28. P.A. Beerel and M.E. Roncken, "Low Power and Energy Efficient Asynchronous Design," J. Low Power Electronics, vol. 3, no. 3, 2007, pp. 234-253.
29. P.B. McGee et al., "A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication," Proc. 14th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 08), IEEE CS Press, 2008, pp. 116-127.
30. G. Gill et al., "A High-Speed GCD Chip: A Case Study in Asynchronous Design," Proc. IEEE Computer Society Ann. Symp. VLSI, IEEE CS Press, 2009, pp. 205-210.
31. G. Gill and M. Singh, "Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems," Proc. IEEE Symp. Asynchronous Circuits and Systems (ASYNC 10), IEEE CS Press, 2010, pp. 117-127.
32. P. Prakash and A.J. Martin, "Slack Matching Quasi Delay-Insensitive Circuits," Proc. 12th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 195-204.
33. G. Gill et al., "Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines," Proc. 12th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 46-56.
34. O.A. Petlin and S.B. Furber, "Scan Testing of Micropipelines," Proc. 13th IEEE VLSI Test Symp. (VTS 95), IEEE CS Press, 1995, pp. 296-301.
35. J. Cortadella et al., "Desynchronization: Synthesis of Asynchronous Circuits from Synchronous Specifications," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, 2006, pp. 1904-1921.
1. A.M. Lines, Pipelined Asynchronous Circuits, tech. report, Dept. of Computer Science, California Inst. of Technology, 1998.
2. S.B. Furber and J. Liu, "Dynamic Logic in Four-Phase Micropipelines," Proc. 2nd Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 96), IEEE CS Press, 1996, pp. 11-16.
3. M. Singh and S.M. Nowick, "The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 1256-1269.
4. M. Singh and S.M. Nowick, "The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, 2007, pp. 1270-1283.
5. J. Ebergen et al., "GasP Control for Domino Circuits," Proc. 11th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 12-22.
6. M. Ferretti and P.A. Beerel, "High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells," IEEE J. Solid-State Circuits, vol. 41, no. 6, 2006, pp. 1444-1454.
7. A. Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, 2004, pp. 32-41.
8. M. Singh et al., "An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, 2010, pp. 1043-1056.

Index Terms:
design and test, asynchronous, pipelines, elastic circuits, dynamic logic, micropipelines, latch controllers
Citation:
Steven M. Nowick, Montek Singh, "High-Performance Asynchronous Pipelines: An Overview," IEEE Design & Test of Computers, vol. 28, no. 5, pp. 8-22, Sept.-Oct. 2011, doi:10.1109/MDT.2011.71
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