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Issue No.05 - September/October (2011 vol.28)
pp: 2
Published by the IEEE Computer Society
ABSTRACT
<p>This special issue introduces <it>Design &#x0026; Test</it> readers to several key developments and the landscape of recent research in asynchronous design.</p>




I remember asynchronous systems always being talked about as an attractive alternative to mainstream synchronous system design. In recent years, as chips got bigger, wires got longer, and interconnect delays started to become a headache, designers began showing renewed interest in asynchronous (clockless) systems. Designers of synchronous chips today have to grapple with the problems of high-speed clock distribution, high power consumption, integration of multiple cores operating at different speeds, process variations, and so on. It's therefore not surprising that asynchronous designs are now seeing wider adoption; they rely on handshaking instead of complex clocking schemes, and therefore reduce unnecessary switching activity and accommodate delay variations.
Today's ubiquitous core-based systems-on-chip designs have a multiplicity of distinct clock domains, and the interaction between these clock domains is often asynchronous in nature. Moving forward, asynchronous design is likely to be the best choice for emerging nanotechnologies, which are expected to suffer from high process variations and aren't amenable to centralized (synchronous) control. Asynchronous design has already been demonstrated in a number of mainstream applications, ranging from gigahertz PGAs to terabit-rate network switches and low-power processors for e-passports and smart cards.
This special issue introduces D&T readers to several key developments in asynchronous design and the landscape of recent research in this area. It includes two tutorial articles by leading experts on performance boosting using asynchronous pipelines, and metastability in asynchronous systems and its mitigation using synchronizers. The issue also includes three case study articles on the design of delay-insensitive dynamic gates, asynchronous CAD tools for automated synthesis and physical design; globally asynchronous, locally synchronous design; and applications to cryptography. The last two articles in the special issue highlight the role asynchronous design can play in emerging technologies such as quantum cellular automata and energy harvesting.
Guest Editors Luciano Lavagno and Montek Singh have done a commendable job in soliciting papers for this issue. The special issue solicitation received a large number of high-quality submissions, and the guest editors handled the heavy workload with diligence and sincerity, without any lapse in the tight schedule. I thank Luciano and Montek for serving as guest editors, the authors for their contributions, and the reviewers for their diligence, and adherence to schedules, and commitment to D&T.
This issue also includes a roundtable discussion: "Can We Trust the Chips of the Future?" Roundtables have always been an exciting and popular feature of D&T, and in this issue we address the growing concern of cybersecurity and how it relates to the design of trustworthy ICs. A panel of experts was invited to participate in a roundtable at the Design Automation Conference in June 2011; they discussed major problems in hardware security and trust, and highlighted some of the solutions that are currently available.
Finally, the special issue includes a comprehensive review of a recently published book on Property Specification Language, which is an industry-standard assertion language for hardware specification. Nicolas Troquard explains how this book can be invaluable for hardware verification, one of the key contributors to long design cycles.
Krishnendu Chakrabarty
Editor in Chief
IEEE Design & Test




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