The Community for Technology Leaders
RSS Icon
Issue No.04 - July/August (2011 vol.28)
pp: 88-97
Shi-Yu Huang , Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Nat. Tsing Hua Univ., Hsinchu, Taiwan
Shyue-Kung Lu , Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.
logic testing, fault diagnosis, field programmable gate arrays, integrated circuit testing, fault-injection scan chain, emulation-based diagnosis technique, logic cores, FPGA-based emulation system, IC fault diagnosis, circuit partitioning, fault-injection element, Circuit faults, Emulation, Fault diagnosis, Logic gates, Benchmark testing, Field programmable gate arrays, fault-injection scan chain, design and test, logic diagnosis, fault emulation, fault injection, circuit partitioning
Shi-Yu Huang, Cheng-Wen Wu, Shyue-Kung Lu, "Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores", IEEE Design & Test of Computers, vol.28, no. 4, pp. 88-97, July/August 2011, doi:10.1109/MDT.2011.25
1. R. Ubar et al., "Fault Diagnosis in Integrated Circuits with BIST," Proc. 10th Euromicro Conf. Digital System Design Architecture, Methods and Tools (DSD 07), IEEE CS Press, 2007, pp. 604-610.
2. I. Pomeranz and S.M. Reddy, "On Dictionary-Based Fault Location in Digital Logic Circuits," IEEE Trans. Computers, vol. 46, no. 1, 1997, pp. 48-59.
3. I. Pomeranz and S.M. Reddy, "Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning," IEEE Trans. Computers, vol. 47, no. 10, 1998, pp. 1124-1134.
4. A. Parreira, J.P. Teixeira, and M.B. Santos, "Built-In Self-Test Quality Assessment Using Hardware Fault Emulation in FPGAs," Computing and Informatics, vol. 23, nos. 5–6, 2004, pp. 1001-1020.
5. P. Civera et al., "New Techniques for Efficiently Assessing Reliability of SOCs," Microelectronics J., vol. 34, no. 1, 2003, pp. 53-61.
6. C. López-Ongil et al., "Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation," IEEE Trans. Nuclear Science, vol. 54, no. 1, 2007, pp. 252-261.
7. A. Ejlali and S.G. Miremadi, "FPGA-Based Fault Injection into Switch-Level Models," Microprocessors and Microsystems, vol. 28, nos. 5–6, 2004, pp. 317-327.
8. P. Civera et al., "Exploiting Circuit Emulation for Fast Hardness Evaluation," IEEE Trans. Nuclear Science, vol. 48, no. 6, 2001, pp. 2210-2216.
9. K.T. Cheng, S.Y. Huang, and W.J. Dai, "Fault Emulation: A New Methodology for Fault Grading," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, 1999, pp. 1487-1495.
10. S.A. Hwang, J.H. Hong, and C.W. Wu, "Sequential Circuit Fault Simulation Using Logic Emulation," IEEE Trans. Computer-Aided Design, vol. 17, no. 8, 1998, pp. 724-736.
11. F. Kocan and D.G. Saab, "Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware," J. Electronic Testing: Theory and Applications, vol. 23, no. 5, 2007, pp. 405-420.
12. P. Civera et al., "An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits," J. Electronic Testing: Theory and Applications, vol. 18, no. 3, 2002, pp. 261-271.
64 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool