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| Florent de Dinechin, Bogdan Pasca, "Designing Custom Arithmetic Data Paths with FloPoCo," IEEE Design & Test of Computers, vol. 28, no. 4, pp. 18-27, July/August, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2011.44, author = {Florent de Dinechin and Bogdan Pasca}, title = {Designing Custom Arithmetic Data Paths with FloPoCo}, journal ={IEEE Design & Test of Computers}, volume = {28}, number = {4}, issn = {0740-7475}, year = {2011}, pages = {18-27}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2011.44}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Designing Custom Arithmetic Data Paths with FloPoCo IS - 4 SN - 0740-7475 SP18 EP27 EPD - 18-27 A1 - Florent de Dinechin, A1 - Bogdan Pasca, PY - 2011 KW - design and test KW - FloPoCo KW - core generator KW - arithmetic circuit KW - floating-point KW - pipelining KW - data path KW - FPGAs KW - reconfigurable computing KW - VHDL KW - C++ framework VL - 28 JA - IEEE Design & Test of Computers ER - | |||
Efficient implementation of basic, data-path circuit elements is of fundamental importance to achieving high performance in FPGA-based acceleration of scientific computing. This work presents a leading effort to automate the production of pipelined data-path circuits for implementing numerical functions.
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