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Issue No.03 - May/June (2011 vol.28)
pp: 94-95
Published by the IEEE Computer Society
ABSTRACT
<p>This month's DATC newsletter features A Message from the Chair (David Kung), a Message from the Editor (Joe Damore), and upcoming conferences of interest to the DATC community.</p>
A Message from the Chair
In his new book, Physics of the Future, Michio Kaku, professor of theoretical physics and a "popularizer" of science, boldly predicted that Moore's law will end around 2020, wreaking havoc not only on the semiconductor industry but also on the global economy. While this doomsday scenario might not be realized in a decade—we still have a few more generations to go—Moore's law cannot last forever. First of all, although at times it may seem otherwise, it is not CEOs but physics that rules the universe. When there are only a handful of atoms in a layer of material, quantum mechanics takes over, which means that the characteristics of a transistor will have so much variability that it will not be useful as a switch.
Then there is the economic factor. It has been reported in EE Times that the price tag for EUV lithography, the belated next-generation litho tool that could sustain Moore's law, is estimated to be $125 million per tool. Only a few behemoths that thrive on very high volume or exorbitant margins can afford to invest in this technology. Therefore, even before the demise of Moore's law, a large segment of the electronics industry will stay at a technology node for a very long time.
The question is, if the industry cannot extract any more gain from the underlying technology, at least until the replacement technology comes along, what can it leverage to deliver performance and benefit to the customers so that they will continue to upgrade, buy new products, and drive the economy forward? And, what's more important, what can the design automation community do to help?
The situation is not as dire as I have portended. Customers are basically agnostic to Moore's law: they care about how much benefit they are getting but not where the benefits are derived from. As long as applications run faster and better, customers will keep investing in the next generation of information technology.
One interesting way to deliver more performance and power efficiency is the use of FPGAs to accelerate specific functions for which general-purpose processors are not optimized. Unfortunately, FPGAs are programmed using hardware description languages, which have a wide semantic gap with popular object-oriented languages such as C++ and Java, and therefore rendering FPGAs largely inaccessible by software developers. The ideal situation is to have one unified language—working across multicore CPUs and their accelerators—in conjunction with a high-level synthesis capability that "optimally" partitions the workload seamlessly between the CPUs and the accelerators. Several vendors as well as industry research organizations have been working toward this goal. The design automation community has a lot of expertise to help in this effort: software/hardware codesign, general high-level synthesis, and logic synthesis, for example. Therefore, I am soliciting interest in starting a new initiative within the DATC to further research in this direction. If anyone is interested in contributing to this effort, please send me email at kung@us.ibm.com.
P. S. The DATC is also organizing a "DA and Smart Grid II" workshop at the Design Automation Conference in San Diego on 9 June 9 2011, which is the follow-up to the DA and Smart Grid workshop in 2010. We have invited a lot of leaders from the power and energy community to speak and interact with us, so please save the date. I will send out more details very soon.
David S. Kung
DATC Chair
Senior Manager, Design Automation
IBM T.J. Watson Research Center
914-945-3183
kung@us.ibm.com
Message from the Editor
Please visit our website at http://www.datc.info, which has links to all our phone meeting minutes as well as our Newsletter and many other topics. Please take some time to critique the site; I would love some suggestions.
Joe Damore
Newsletter Editor
Calendar
44th IEEE International Symposium on Circuits and Systems (ISCAS 2011)
15–18 May 2011
Rio de Janeiro
http://www.iscas2011.org
48th Design Automation Conference (DAC 2011)
5–9 June 2011
San Diego
http://www.dac.com/
3rd Asia Symposium on Quality Electronic Design (ASQED 2011)
19–20 July 2011
Kuala Lumpur, Malaysia
http://www.asqed.com
Forum on Specification and Design Languages (FDL 2011)
13–15 September 2011
Oldenburg, Germany
http://www.ecsi.org/fdl
2011 Conference on Design and Architectures for Signal and Image Processing (DASIP 2011)
2–4 November 2011
Tampere, Finland
http://www.ecsi.org/dasip
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