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Improving Analog and RF Device Yield through Performance Calibration
May/June 2011 (vol. 28 no. 3)
pp. 64-75
Nathan Kupp, Yale University
He Huang, Yale University
Yiorgos Makris, Yale University,
Petros Drineas, Rensselaer Polytechnic Institute

As the semiconductor industry continues scaling devices toward smaller process nodes, maintaining acceptable yields despite process variations has become increasingly challenging. Analog and RF circuits are particularly sensitive to process variations. This article discusses the challenges of cost-effective postfabrication performance calibration in such analog and RF devices and introduces a single-test, single-tuning-step method to constrain cost and complexity while reaping the benefits of a tunable design.

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Index Terms:
design and test, analog and RF, postfabrication performance calibration, tuning, yield
Citation:
Nathan Kupp, He Huang, Yiorgos Makris, Petros Drineas, "Improving Analog and RF Device Yield through Performance Calibration," IEEE Design & Test of Computers, vol. 28, no. 3, pp. 64-75, May-June 2011, doi:10.1109/MDT.2010.119
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