The Community for Technology Leaders
RSS Icon
Issue No.03 - May/June (2011 vol.28)
pp: 54-63
Ilia Polian , University of Passau
<p>As ICs shrink into the nanometer range, they are increasingly subject to errors induced by physical faults. Traditional hardening for error mitigation consumes too much area and energy to be cost-effective in commercial applications. Selective hardening, applied only to a design's most error-sensitive parts, offers an attractive alternative. This article reviews recently proposed techniques to selectively harden nanoelectronics and achieve very low error levels.</p>
design and test, selective hardening, soft errors, reliability, fault tolerance, error tolerance
Ilia Polian, "Selective Hardening: Toward Cost-Effective Error Tolerance", IEEE Design & Test of Computers, vol.28, no. 3, pp. 54-63, May/June 2011, doi:10.1109/MDT.2010.120
1. B. Bhushan ed., Springer Handbook of Nanotechnology, 3rd ed., Springer, 2010.
2. I. Koren and C.M Krishna, Fault-Tolerant Systems, Morgan Kaufmann, 2007.
3. M. Fazeli et al., "Low Energy Single Event Upset/Single Event Transient-Tolerant Latch for Deep Submicron Technologies," IET Computers & Digital Techniques, vol. 3, no. 3, 2009, pp. 289-303.
4. A.K. Nieuwland, S. Jasarevic, and G. Jerin, "Combinational Logic Soft Error Analysis and Protection," Proc. 12th IEEE Int'l On-Line Testing Symp. (IOLTS 06), IEEE CS Press, 2006, pp. 99-104.
5. I. Polian and W. Rao, "Selective Hardening of NanoPLA Circuits," Proc. 23rd IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFTS 08), IEEE CS Press, 2008, pp. 263-271.
6. S. Baranov et al., "Designing Fault Tolerant FSM by Nano-PLA," Proc. 15th IEEE Int'l On-Line Testing Symp. (IOLTS 09), IEEE CS Press, 2009, pp. 229-234.
7. V. Izosimov et al., "Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors," Proc. Design, Automation and Test in Europe Conf. (DATE 09), European Design Automation Assoc., 2009, pp. 682-687.
8. M.A. Breuer, "Multi-media Applications and Imprecise Computation," Proc. 8th Euromicro Conf. Digital System Design (DSD 05), IEEE CS Press, 2005, pp. 2-7.
9. D. Nowroth, I. Polian, and B. Becker, "A Study of Cognitive Resilience in a JPEG Compressor," Proc. IEEE Int'l Conf. Dependable Systems and Networks with FTCS and DCC (DSN 08), IEEE Press, 2008, pp. 32-41.
10. S.A. Seshia, W. Li, and S. Mitra, "Verification-Guided Soft Error Resilience," Proc. Design, Automation and Test in Europe Conf. (DATE 07), EDA Consortium, 2007, pp. 1442-1447.
11. I. Polian et al., "Low-Cost Hardening of Image Processing Applications against Soft Errors," Proc. 21st IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFTS 06), IEEE CS Press, 2006, pp. 274-279.
12. J.P. Hayes, I. Polian, and B. Becker, "An Analysis Framework for Transient-Error Tolerance," Proc. 25th IEEE VLSI Test Symp. (VTS 07), IEEE CS Press, 2007, pp. 249-255.
17 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool